Many methods are known for forming the electrical interconnections between an integrated circuit and the supporting substrate. Tape automated bonding (TAB) methods are commonly used for forming these such electrical interconnections. A TAB tape is provided which comprises a plurality of individual long, slender, electrically conductive leads attached to, and extending out from, the electrically conductive TAB tape. Each individual lead on the TAB tape is bonded to the integrated circuit at a bonding pad. There are typically many of these bonds on a single integrated circuit. These bonds are formed by first depositing a gold bump, or other suitable material, on either the end of the TAB tape lead or on the integrated circuit at the bonding pad. The integrated circuit and TAB tape leads, which are generally copper, are then aligned and simultaneously thermocompression gang bonded.
However, with any of these methods for forming the electrical interconnections, strain relief must be provided in the interconnection lead between the integrated circuit and supporting substrate, so as to compensate for any thermal or physical stresses arising during use. For example, when using tape automated bonding methods for forming the electrical interconnections, strain relief is commonly provided by forming the individual TAB tape leads in a serpentine manner, as shown in FIG. 1. The use of the serpentine shape essentially provides additional length to the individual lead, thereby permitting expansion of the individual leads to compensate for any stresses arising during use.
However, a shortcoming associated with the use of these individual serpentine leads is that the associated stresses generated during use become unbalanced due to the various serpentine lead lengths and the positioning of each serpentine lead from different directions around the integrated circuit. This unbalanced state results in higher failure rates for the individual bonds on the integrated circuit and correspondingly for the device. In addition, the current serpentine design results in increased lead stress during mounting of the integrated circuit to a substrate or other surface, since the various lengths of each lead again result in an unbalanced stress load during mounting.
An alternative to the current serpentine design for electrical interconnections, which provides for improved and balanced stress relief during use and mounting of the integrated circuit, is disclosed in U.S. Ser. No. 07/448,453 to Eytcheson, filed Dec. 11, 1989, entitled "Interconnection Lead Having Individual Spiral Lead Design", and assigned to the same assignee of the present invention. In Eytcheson, an interconnection pattern is taught having individual leads which are arcuate shaped and disposed in a spiral pattern around the integrated circuit. This spiral interconnection pattern provides improved strain relief over the conventional serpentine design, since the individual, arcuate shaped electrical leads all expand in a spiral pattern, thereby causing the integrated circuit to rotate in a single direction when a stress is applied to the integrated circuit. The resulting stress loads are therefore more balanced than with previous lead designs.
However, although the spiral design provides enhanced strain relief, a shortcoming exists with regard to its use. The arcuate shapes of the individual electrical leads do not permit the most efficient utilization of the space on and around an integrated circuit chip. Therefore, the number of electrical interconnection leads per integrated circuit is limited. As the complexity of integrated circuits increases while their physical dimensions decrease, it is of prime importance to provide an interconnection lead which permits maximization of the number of leads per integrated circuit.
Therefore, what is needed is an electrical interconnection lead which provides for, not only balanced stress relief during use and mounting of the integrated circuit, but which also provides an efficient design for maximization of the number of individual leads available per integrated circuit.